The present invention relates to the art of electronic packaging and more particularly to a microelectronic package with enhanced thermal performance.
Ball grid array (BGA) packages for integrated circuits are widely used in the semiconductor packaging industry. Since BGAs use area array contacts, instead of conventional perimeter leads, the physical size of high pin count packages can be significantly reduced. The relatively large pitch size in conventional BGAs requires large package bodies to accommodate high input/output terminal (I/O) applications. To further reduce the size of the packages and accommodate high I/O applications, near chip size BGAs (BGAs which are nearly the size of the integrated circuit that is packaged) have recently been developed.
DiStefano, xe2x80x9cReliable BGAs emerge in micro formxe2x80x9d, Electronic Engineering Times Pg. 104, 111 (September 1994) discusses a near chip size BGA developed by Tessera(copyright) Inc. (Tessera(copyright) xcexcBGA(trademark)). FIG. 1 is a cross-sectional view of a similar BGA 11. In FIG. 1, an integrated circuit 10 has a first surface 22 with a plurality of bonding pads 12 thereon. Bond pads 12 are connected to a plurality of metallizations or traces 16 on a substrate 14 by electrical connectors 18 such as bond wires. Bumps or balls 20 are formed on each trace 16 to enable electrical connections between BGA 11 and other electrical components. A compliant elastomeric layer 15 is located between integrated circuit 10 and substrate 14. Compliant elastomeric layer 15 is attached directly to the first surface 22 of integrated circuit 10 with silicone encapsulant material 19. Integrated circuit 10 is bonded using a layer of adhesive 24 to a thermal spreader 26. Connectors 18 are encapsulated to complete the fabrication of BGA 11.
Compliant elastomeric layer 15 compensates for or takes up the difference in the thermal coefficient of expansion (TCE) between integrated circuit 10 and substrate 14. Compliant elastomeric layer 15 is required because substrate 14, formed of flexible polyimide film, has a relatively high thermal expansion rate compared to the thermal expansion rate of integrated circuit 10. By accommodating for TCE mismatch, compliant elastomeric layer 15 provides protection against stress related problems such as warping and solder ball cracking. However, since compliant elastomeric layer 15 is an elastomer and elastomers are poor thermal conductors, heat transfer from integrated circuit 10 through first surface 22 is inhibited. Yet it is desirable to enhance heat transfer from integrated circuit 10. Further, elastomers have a tendency to absorb moisture from the ambient environment leading to delamination of compliant elastomeric layer 15 and ultimately to the failure of BGA 11.
It is desirable to form an integrated circuit package that is approximately the size of the integrated circuit. Further, as the art moves towards integrated circuits which consume more power, it becomes increasingly important that heat from the integrated circuit package is readily dissipated to the ambient environment. Further, the integrated circuit package should be resistant to environmental degradation.
In accordance with the invention, a thermally enhanced package for a semiconductor device, the semiconductor device having a first surface with bond pads formed thereon, includes a heat sink structure attached to a central region of the first surface of the semiconductor device inward of the bond pads. The package further includes an electrically insulative substrate having a first surface attached to the heat sink structure. The heat sink structure includes a heat sink, a first layer of adhesive between the heat sink and the first surface of the semiconductor device and a second layer of adhesive between the heat sink and the first surface of the substrate. By forming the heat sink structure with a heat sink, heat transfer between the first surface of the semiconductor device and the substrate is enhanced compared to the prior art.
Further, the first and second adhesive layers decouple any difference in thermal expansion/contraction (i.e. decouple any TCE mismatch) between the semiconductor device, the heat sink and the substrate. This increases the reliability of the package as well as any bonds formed between the package and another electronic structure such as a printed circuit board. Also, the first and second adhesive layers avoid the necessity of a compliant elastomeric layer of the prior art and the associated unreliability, e.g. moisture related problem such as delamination of the compliant elastomeric layer.
In accordance with another embodiment of the present invention, a thermally enhanced package for a semiconductor device includes a heat sink structure which is a mixture of a first component and a second component. The first component (e.g. adhesive) is for decoupling thermal stress (TCE mismatch) between the semiconductor device and the substrate and the second component (e.g. diamond, aluminum nitride or silver powder filler) is for enhancing heat transfer from the first surface of the semiconductor device to the substrate.
In accordance with the present invention, a method of fabricating thermally enhanced packages for semiconductor devices includes providing a strip-like tape comprising a plurality of electrically insulative substrates. Each of the substrates has a first surface with a heat sink structure and electrically conductive traces attached thereto. Central regions of first surfaces of the semiconductor devices are then attached to the heat sink structures and the traces are then electrically connected to the bond pads. A coverlay is applied to a first surface of the tape and thereby to second surfaces of the substrates. An encapsulant is applied to enclose the bond pads and sides of the heat sink structures and then the coverlay is removed. After interconnect balls are formed on portions of the traces and in apertures in the substrates, the tape is cut to singulate the packages.
These and other objects, features and advantages of the present invention will be more readily apparent from the detailed description of the preferred embodiments set forth below taken in conjunction with the accompanying drawings.